Comparator of phase between a digital signal and a clock signal, and corresponding phase locked loop
US5602512A · kind A · utility
7Cited by
3References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 6, 1995 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Dec 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator of phase between a digital signal and a clock signal adapted for the construction of a phase locked loop in integrated circuit form, that includes a first channel formed by a flip-flop and an exclusive OR gate, and a second channel formed by a second exclusive OR gate and a delay circuit whose delay is set to half the period of the clock signal. The first channel receives the digital signal and the clock signal and delivers a first detection signal of transition of the digital signal. The second channel receives only the digital signal and delivers a second detection signal of transition of the digital signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.