Patent · US Expired

Method of and device for forming the sum of a chain of products

US5602766A · kind A · utility

6Cited by

4References

14Claims

0Family size

Assignee

U.S. Philips Corporation · US

Inventors

Harald Bauer · Ehningen, DE
Johannes Schuck · Westerburg, DE
Karl Hellwig · Wonfurt, DE
Dietmar Lorenz · Erlangen, DE

Key dates

Filing date	Feb 1, 1994
Grant date	Feb 11, 1997
Priority date	—
Expiry date	Feb 1, 2014

Classification

Technology area (CPC G)Physics
CPC primaryG06F7/5443
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Digital signal processing often requires the fast summing of a chain of products. Known signal processors often use two separate dam buses via which the values to be multiplied are supplied in parallel, it being assumed that these values originate from different sources, for example from different memories. Because a product of two binary numbers has double the number of positions, therefore, an adder having double the word width is also used. In order to reduce this substantial expenditure at the expense of only a slight reduction in speed, an adder is provided having only the single word width and to process the most-significant and least-significant bits of the product during two successive clock periods. The values to be multiplied can then be supplied successively.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.