Serial to parallel and parallel to serial architecture for a RAM based FIFO memory
US5602780A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1993 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Oct 20, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FIFO memory (4) provides serial to parallel and parallel to serial data conversion. A read frame buffer (40) and a write frame buffer (30) are coupled with a RAM array (22). Serial input data is stored temporarily into the write frame (30) of fixed width, n bits wide. Then, the entire n bit wide frame of stored serial input data is written into RAM array (22) at once in parallel. Data read in parallel from RAM array (22) is stored temporarily into the read frame (40) and thereafter provided serially to the FIFO output (53). By converting serial input to parallel input, overall chip size is reduced by reducing the number of pointers required because it is not necessary to address the RAM (22) individually when serially writing data into it. The read frame (40) coupled to the write frame (30) and to the serial input data. This allows data written into the FIFO to be immediately available and allows the read frame (40) to receive backfilled data from the write frame (30).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.