Protect path switching in a performance monitoring and test system
US5602828A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1995 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | May 26, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M3/244
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.