Error correction method and apparatus
US5602857A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1994 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Oct 18, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error correction system (1000) included in a utilization device (1002) operates upon a plurality of sectors (S) stored in a data buffer (1100) for performing write-from-host and read-from-device operations. Overlapping and asynchronous operational steps are performed with respect to the plurality of sectors, the operational steps including sector transfer into buffer, sector correction, and sector transfer out of buffer. The error correction system (1000) includes a plurality of subsystems which are supervised and sequenced by correction controller (1020). The subsystems include a CRC generation and checking subsystem (1030); an LBA subsystem (1040); an ECC/Syndrome Generator subsystem (1050); a header (ID) subsystem (1060); a correction subsystem (1070); and, a correction checker system (1075).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.