Semiconductor disk system having a plurality of flash memories
US5603001A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1995 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | May 5, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0664
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND bus interface independently receives 16 ready/busy signals from 16 flash EEPROM chips and thereby separately manages the operating states of these flash EEPROMs. Once a flash EEPROM as a write access target is set in a ready state, a write access to this write access target flash EEPROM is started without waiting for completion of the operations of all the flash EEPROMs. Each flash EEPROM is of a command control type capable of automatically executing a write operation. This allows parallel processing of the flash EEPROMs, i.e., a write access to a given EEPROM can be performed while a data write to another flash EEPROM is being executed. An ECC calculating circuit calculates a data string transferred in units of 256 bytes from a data buffer by a processor, and generates an ECC corresponding to that data string. The 256-byte data string is added with the generated ECC and transferred to a data register of a flash EEPROM. Even if abnormal cells are produced at the same bit position in a plurality of pages of a flash EEPROM, only one abnormal cell is contained in a data string as an object of the ECC calculation. This makes it possible to perform error detection and correction…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.