Computer system having cache memories with independently validated keys in the TLB
US5603008A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1994 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Nov 10, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage unit for a data processing system includes a cache data buffer, a cache tag, and a translation lookaside buffer (TLB). Storage keys are maintained in the TLB with a separate valid bit, which allows a valid translation to be stored upon completion of a translation, even though the key is not yet available. With a valid translation in the TLB entry available, the requesting port is then able to send off a move in request to mainstore right away in parallel with a key request from the translator to the mainstore key array. In the typical case, the key will be returned several cycles ahead of the data, allowing it to be written into the TLB entry and validated in time for the move in data to be successfully bypassed to the requestor as soon as it arrives.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.