Selective shadowing and paging in computer memory systems
US5603011A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 1994 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Nov 18, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0638
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Principal data (e.g. frequently accessed data such as video BIOS program information and a principal font set) and secondary data (e.g. secondary font sets) are permanently stored in a slow memory device (e.g. EPROM). To improve performance, the principal data but not the secondary data is copied initially to a faster access memory device (shadow RAM). Translating logic associated with the latter device is initially configured to intercept memory requests, having addresses in a range preassigned to the EPROM, and redirect them to shadow RAM. However, in order to allow for access to the secondary data, the redirection function of the translating logic can be disabled and re-enabled, under control of programs running in an associated computer, so that requests in the preassigned address range are routed directly to the EPROM. When the translating logic is disabled, all of the EPROM becomes accessible including locations containing the principal data and locations containing the secondary data. When the translating logic is enabled, only the principal data in the shadow RAM is accessible. The disabling and re-enabling functions are implemented presently by means of unique function cal…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.