Channel module for a fiber optic switch with bit sliced memory architecture for data frame storage
US5603064A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 27, 1994 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Oct 27, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/122
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A channel module has an interchangeable port intelligence system at a front end which is connected to a memory interface system at a back end. Each port intelligence system provides one or more ports for connection to fiber optic channels and, the various port intelligence systems are distinguishable by a particular bit rate in which each supports. Data from the port intelligence system is bit sliced and forwarded to the memory interface system. In the system, the data is stored in receive memory in a distributed manner over a plurality of receive memory components. The bit slicing simplifies the input/output interface to the receive memory and enables storage of data with a common format, regardless of the rate at which the data was received from the channel. When data is read from the receive memory, each of the receive memory components contributes bits in order to reconstruct the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.