Memory structure with multiple integrated memory array portions
US5604518A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1994 |
| Grant date | Feb 18, 1997 |
| Priority date | — |
| Expiry date | Mar 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory structure, and associated processing method, is coupled to receive address data and control data. The memory structure includes a composite memory array having a first array portion and a second array portion which are separately addressable. The first array portion is accessed using at least some of the address data as a first address signal and the second array portion is addressed using at least some of the control data also as a second address signal. The memory structure is presented herein by way of example for a serial palette digital-to-analog (SPD) device, and incorporates indirect color mode, direct color mode, overlay color mode and cursor color mode processing in a single macro. When in direct color mode, access to the memory array is disabled and address data is transferred directly to an output of the memory structure as data out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.