Dynamic redundancy circuit for memory in integrated circuit form
US5604702A · kind A · utility
27Cited by
8References
44Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 15, 1994 |
| Grant date | Feb 18, 1997 |
| Priority date | — |
| Expiry date | Sep 15, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To prompt a repairing operation as and when defective cells appear in an integrated circuit memory, there is provided an auxiliary memory related to a programmable comparator. Whenever the cells of the memory are to be read, the auxiliary memory is read and its content is compared with the address selected in the memory array. The result of this comparison produces, in real time, the addressing signals of a redundant cell and signals for the neutralization of the initially encountered cell. This system can be used more particularly in the field of EEPROM type memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.