Low power high voltage switch with gate bias circuit to minimize power consumption
US5604711A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 19, 1995 |
| Grant date | Feb 18, 1997 |
| Priority date | — |
| Expiry date | May 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit with a low power programming voltage switch for reduced leakage current during a read operation. The apparatus includes a high voltage switch which, in a programming mode receives a high (e.g. programming) voltage and in another mode (reading) receives a normal range voltage, and a line driver which drivers a selection or non-selection voltage into word lines or column select lines into a memory array. During a read mode, the deselected line drivers and high voltage switches are operated in a reduced leakage current mode such that leakage current is forced through selected line drivers and their high voltage switches before being forced through the deselected line drivers such that the leakage current is limited to the number of selected line drivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.