Method and apparatus for removably connecting either asynchronous or burst cache SRAM to a computer system
US5604875A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1994 |
| Grant date | Feb 18, 1997 |
| Priority date | — |
| Expiry date | Dec 19, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache SRAM connector assembly comprising a connector, a number of latches, and a number of high performance switches, is provided to a computer system. The connector removably connects either asynchronous or burst cache SRAM to a processor bus. The latches store cache access addresses being driven on a number of address lines of the processor bus. The high performance switches being coupled to both the latches and the address lines of the processor bus selectively provide the cache SRAM with latched access addresses as required by asynchronous cache SRAM or directly driven access addresses on the processor bus as required by burst cache SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.