Computer system with a memory identification scheme
US5604880A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 7, 1996 |
| Grant date | Feb 18, 1997 |
| Priority date | — |
| Expiry date | May 7, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system having a central processing unit (CPU) coupled to a memory, a method is described for identifying whether the memory is a first type of memory or a second type of memory. A programming voltage is decoupled from a control circuit of the memory such that the control circuit is disabled from accessing a memory array of the memory during a write operation of the memory. The memory is then accessed from the CPU through the write operation for a device identification from the memory. The first type of memory includes the device identification and the second type of memory does not include the device identification. Data integrity of the memory is maintained during the write operation because the memory array of the memory is not accessed during the operation. The memory is then identified as the first type of memory if the CPU receives the device identification from the memory. The memory is identified as the second type of memory if the CPU does not receive the device identification from the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.