Apparatus for processing instructions in a computing system
US5604909A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1993 |
| Grant date | Feb 18, 1997 |
| Priority date | — |
| Expiry date | Dec 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. A bypass circuit for bypassing the second instruction storing circuit is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.