Phase locked loop circuit current mode feedback
US5604926A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1995 |
| Grant date | Feb 18, 1997 |
| Priority date | — |
| Expiry date | Mar 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D13/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) circuit for use as a demodulator and other applications. The PLL circuit (200) comprises a phase detector (210), a transconductance amplifier (212) and a current controlled oscillator (ICO) (214). The phase detector has two signal inputs and two outputs, and detects a phase difference between signals at its inputs. A capacitor C1 is connected to the output of phase detector (210) and develops an output voltage signal vo(t). A transconductance amplifier (212) is coupled to the capacitor C1 and converts the output voltage signal vo(t) to an output current signal. The ICO (214) is coupled to the transconductance amplifier (212) and the second output of the phase detector (210) and generates an output signal having a frequency which is proportional to an input current signal. The output signal of the ICO (214) is coupled to the second signal input of the phase detector (212).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.