Programmable logic array integrated circuits with enhanced output routing
US5606266A · kind A · utility
86Cited by
8References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1995 |
| Grant date | Feb 25, 1997 |
| Priority date | — |
| Expiry date | Jun 30, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). A general interconnect structure (20, 30) is provided for interconnecting a LAB with other LABs. A LAB-based interconnect structure (24, 26) is provided for connecting inputs of the LEs in a LAB to a subset of the general interconnect. One or more of output signal lines (55) are included in the LAB-based interconnect structure and are connectable to device output pins. A digital information processing system incorporating the invention is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.