Serial port using non-maskable interrupt terminal of a microprocessor
US5606671A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1994 |
| Grant date | Feb 25, 1997 |
| Priority date | — |
| Expiry date | Nov 4, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial port which transmits a start bit of a serial transmission to a non-maskable interrupt terminal of a microprocessor so as to be certain that the microprocessor responds to serial communication. The serial port includes a microprocessor-writable transmit bit connected to the transmit terminal of the serial port, a microprocessor-readable receive bit connected to the receive terminal of the serial port, and an NMI enable switch connected between the receive terminal and the NMI pin of the microprocessor. In a receive mode, the NMI enable switch which initially is in a conductive state, transmits the start bit of serial transmissions directly to the NMI pin of the microprocessor causing the microprocessor to interrupt on-going processes. The microprocessor disables the NMI enable register and, after waiting for serial transmission periods between transmitted bits, reads all eight data bits received at the receive terminal from the received bit. Thereafter, the microprocessor re-enables the NMI enable switch and resumes the suspended on-going processes. In a transmit mode, the microprocessor writes a binary 1, corresponding to a start bit, to the transmit bit, causing a transmi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.