Method and apparatus for dynamic cache memory allocation via single-reference residency times
US5606688A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1994 |
| Grant date | Feb 25, 1997 |
| Priority date | — |
| Expiry date | Aug 31, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/121
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache having dynamic cache memory allocation is provided. A cache memory stores a plurality of data blocks, each block belonging to one of a plurality of data sets. A cache directory maintains a list of entries associated with the data blocks stored in the cache memory, wherein each entry corresponds to an individual data block and has fields for storing information including a designation of the data set to which the corresponding data block belongs. A directory controller generates each entry when the corresponding data block is loaded in the cache. The directory controller inserts the generated entry into the list at the optimal insertion point for the data block's data set, which is derived from a calculated optimal single-reference residency time for that data set. Further, the directory controller moves an entry in the list to the insertion point for the given data set of a corresponding data block when the corresponding data block is referenced in the cache. A storage control unit for storing data blocks within the cache memory replaces in the cache memory the data block corresponding to the bottom entry of the list with the data block corresponding to an entry inserted in…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.