Integrated data processing system including CPU core and parallel, independently operating DSP module and having multiple operating modes
US5606714A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1995 |
| Grant date | Feb 25, 1997 |
| Priority date | — |
| Expiry date | Dec 1, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure, having a central processing unit (CPU) formed as a part thereof, for configuring the CPU for operating in an operating mode selected from a plurality of possible operating modes. The possible operating modes include a first possible operating mode that operates exclusively on internal memory storage elements, a second possible operating mode that operates exclusively on external memory storage elements via an external bus connected to a first portion of a plurality of general purpose I/O pins, and a third possible operating mode that operates on external memory storage elements via an external bus connected to a second portion of the general purpose I/O pins such that additional external I/O circuitry is necessary to handle I/O transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.