Method for the testing of integrated circuit chips and corresponding integrated circuit device
US5608335A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 1993 |
| Grant date | Mar 4, 1997 |
| Priority date | — |
| Expiry date | Dec 27, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318511
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a method for the testing of integrated circuits on wafers, the testing is facilitated by setting apart a test circuit zone on the wafer. The test circuit zone comprises contact pads to which it is possible to apply the tips of a tester, and also comprises a demultiplexer to transmit test stimuli to one out of N buses at the output of the demultiplexer. The output buses of the demultiplexer extend between the rows of chips on the wafer. Column selection conductors extend between the columns of chips. The demultiplexer and a decoder, both controlled directly by the tester, enable the selection of one chip at a time for testing. The testing tips are not shifted from one chip to the next one. The wafer is then sliced into individual chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.