DNA controller with wrap-around buffer mode
US5608889A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1994 |
| Grant date | Mar 4, 1997 |
| Priority date | — |
| Expiry date | Aug 17, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A direct memory access (DMA) controller having a first mode and a second mode controls communication between a module bus, communicating with a processor and a memory, and an input/output (I/O) bus communicating with an external device. A data controller subsystem stores I/O bus input data to provide module bus output data, and stores module bus input data to provide I/O bus output data. A device address controller subsystem stores a device address from the module bus to provide an I/O device output address to the I/O bus for addressing the external device. A memory addressing subsystem receives module bus input data to form an initial memory address provided to the module bus representing a storage location in the memory. An incrementer increments the initial memory address. In the second mode, the incrementer restarts the memory address at the initial memory address after incrementing the memory address a selected number of addresses above the initial memory address to form a wrap-around buffer in the memory. A transfer counter calculates a transfer count representing the number of selected data groupings of the I/O bus output data written into the memory. A detector detects when…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.