Process for fabricating transistors using composite nitride structure
US5610099A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1994 |
| Grant date | Mar 11, 1997 |
| Priority date | — |
| Expiry date | Jun 28, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In fabricating a source/drain electrode of an integrated circuit transistor and a contact window for it: (1) establishing a structure with a window over the source/drain region next to a gate electrode and isolation structure; (2) establishing a dielectric layer covering the isolation structure, the window, and gate electrode; (3) implanting a moderate concentration of impurities into the source/drain region through said dielectric layer so that the moderate concentration region extends partially under the gate electrode; (4) removing the horizontal portions of the dielectric layer with an anisotropic etch thereby leaving the dielectric on vertical side walls; (5) establishing a region of titanium silicide over the moderately dosed source/drain region and establishing a titanium nitride layer over the isolation structure, windows, and gate electrode; (6) establishing a layer of silicon nitride over the titanium nitride layer; (7) implanting the substrate with a relatively heavier dose of ions through the silicon nitride, titanium nitride, and titanium silicide layers to create a heavier concentration source/drain region intersecting said moderate concentration region, where the hea…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.