Programmable two-line, two-phase logic array
US5610535A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1995 |
| Grant date | Mar 11, 1997 |
| Priority date | — |
| Expiry date | Sep 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable two-line, two-phase logic array has a plurality of inputs, each having two input signals operating in two phases and memory cells provided at an intersection of the input signal lines and output lines corresponding to at least one function that cross the input lines. The memory cells are capable of being written in the fabrication process or by a field programming process that addresses the contact points at which the input and output lines cross. The two-line, two-phase logic circuit can be attained by the same technique as that used for attaining a conventional PLA without designing circuitry based on a conventional synchronous logic beforehand followed by replacing it with a two-line, two-phase circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.