Controlled delay circuit
US5610546A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1993 |
| Grant date | Mar 11, 1997 |
| Priority date | — |
| Expiry date | Dec 9, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Delay circuit comprising a delay cell formed by a current source (I) connected between drain and source of two field-effect transistors (PO, NO) whose gates are connected to each other in order to constitute the input of the cell, and an inverter (INV) linked to one or other of the terminals of the current source (I) according to whether the delay is to affect the leading edge or the trailing edge of the signal to be delayed, a capacitor (C) for defining a delay time (Te) proportional to the power supply voltage and inversely proportional to the current (I) delivered by the current source, being connected between the input of the inverter (INV) and earth, characterized in that it furthermore comprises a circuit (Ci, Cu, S1, S3, AMPLO, P1) for regulating the current delivered by the current source in order to make it proportional to the power supply voltage of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.