Address generator for generating a plurality of addresses to be used in zig-zag scanning of contents of memory array
US5610873A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 1996 |
| Grant date | Mar 11, 1997 |
| Priority date | — |
| Expiry date | Mar 21, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address generator includes an up/down counter driven by a clock to generate a varying output, an increment counter driven by the clock to generate an incrementing output, and a comparator comparing the varying output and the incrementing output and generating a comparing output. A first register is used for storing an initial address therein. A second register is capable of storing a plurality of step size values therein. The second register is connected electrically to the comparator to receive the comparing output and to the up/down counter to receive a least significant bit of the varying output. The second register outputs one of the step size values according to combination of the comparing output and the least significant bit of the varying output. An adder is connected electrically to the registers and generates a new address equal to a sum of the initial address and one of the step size values. The new address is to be stored in the first register so as to replace the initial address in the first register. A scan number detecting unit controls the up/down counter to generate the varying output in a first counting direction or in a second counting direction opposite to th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.