Shared buffer memory switch for an ATM switching system and its broadcasting control method
US5610914A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 24, 1995 |
| Grant date | Mar 11, 1997 |
| Priority date | — |
| Expiry date | May 24, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A shared buffer memory switch for an ATM switching system and its broadcasting control method are provided which can guarantee the cell transfer quality defined for each connection by maintaining the sequence order of arrival for each cell even if ordinary and broadcasting cells are mixed. When an input cell is a broadcasting cell, bit map data showing a broadcasting destination information is read from a broadcast registration table 6 based on the routing information derived from a header information of the cell, and an address for storing the cell in the shared buffer memory 3 is written in all the address pointer queues of FIFOs 9- corresponding to all output ports shown in the broadcasting destination information, and the cell is stored in the shared buffer memory 3 with the broadcasting destination information. In reading a cell, an address of the shared buffer memory from which the cell is to be read out is read from the address pointer queue of FIFO 9-, and the cell is output to the corresponding output port. In the case where the cell is a broadcasting cell, the broadcasting destination information attached to the cell is reset for the corresponding output port and the revi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.