Address reduction scheme implementing rotation algorithm
US5611001A · kind A · utility
3Cited by
4References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1991 |
| Grant date | Mar 11, 1997 |
| Priority date | — |
| Expiry date | Dec 23, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0207
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a circuit for rotating a digital image any multiple of ninety degrees, an addressing method which reduces the number of address lines required. The rotation circuit relies on a memory configuation which can access each image pixel in memory individually, and this normally requires a large number of address lines. This invention takes advantage of the periodic nature of the data being accessed to reduce the number of address lines required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.