Method and apparatus for decoding and recoding of addresses
US5611054A · kind A · utility
2Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1995 |
| Grant date | Mar 11, 1997 |
| Priority date | — |
| Expiry date | Dec 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A semiconductor component is described which directs transmission of data. The component comprises of a decoder device coupled to said first memory device capable of decoding an address of said data in said first format using said stored address in said first memory device. The component also comprises a translator device coupled to said second memory device capable of transmitting said address of said data in said second format corresponding to said address of said data in said first format, wherein the second format contains the same amount of information as the first format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.