Address prediction for relative-to-absolute addressing
US5611065A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1994 |
| Grant date | Mar 11, 1997 |
| Priority date | — |
| Expiry date | Sep 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A base address prediction system for predicting one of a plurality of base addresses to be added to a known relative address in order to generate an absolute address. An actual base address determined from the relative address is also generated. The actual base address determination takes longer to generate than the predicted base address determination, and therefore the predicted base address is used to select a base address as long as the prediction is correct. Circuitry exists to compare the predicted base address with the actual base address, and if not equal, the predicted base address will be nullified, and the actual base address will be used. Prediction modes are dependent on whether the relative address indicates an instruction fetch or an operand fetch. Where the relative address indicates an instruction fetch, the prediction will be based on the last base address used, on the assumption that instructions will be contiguous in a single block of memory. Where the relative address indicates an operand fetch, the prediction will only change upon the occurrence of two consecutive incorrect predictions, and the actual base address will be used during incorrect prediction perio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.