Method of manufacturing first and second memory cell arrays with a capacitor and a nonvolatile memory cell
US5612238A · kind A · utility
29Cited by
3References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 1996 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | May 1, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM includes a main section including a DRAM memory cell array including a plurality of DRAM cells arranged in an array, a spare section including a Spare DRAM memory cell array including a plurality of DRAM memory cells arranged in an array, an address decoder for specifying addresses respectively of the DRAM memory cell array and the spare DRAM memory cell array, and a defective bit replacement control circuit which is connected to the address decoder and which includes a plurality of electrically rewritable nonvolatile memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.