Insulated gate semiconductor device having a cavity under a portion of a gate structure and method of manufacture
US5612244A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1995 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | Mar 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor substrate (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.