Short circuit power optimization for CMOS circuits
US5612636A · kind A · utility
16Cited by
5References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 19, 1995 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | Jan 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic circuit is constructed from a plurality of logic gates, each logic gate including a logic input, a logic output and a pair of power supply inputs, and each logic gate being operable to permit short circuit current to flow between the power supply inputs thereof during a logic level transition at the logic input thereof. A first logic gate (L) and a second logic gate (D) are provided with the output of the second logic gate connected to the input of the first logic gate, and the drive strength of the second logic gate is selected as a function of the short circuit current permitted by the first logic gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.