Time multiplexed ratioed logic
US5612638A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 17, 1994 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | Aug 17, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A robust family of pre-conditioned complementary CMOS logic elements using scaled MOSFETs and a single clock phase which may be easily interconnected to form high speed logic networks. The family includes both N-type and P-type pre-conditioned logic elements using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFETs according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.