Multiplexer circuit and demultiplexer circuit
US5612695A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1995 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | Feb 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A counter circuit provides select signals SEL0-SEL3 of a cycle 4Tc sequentially attaining a high level for every 1/4 cycle Tc. A 4-input selector circuit receives data signals I0-I3 of a cycle 4Tc to sequentially output the same for every 1/4 period of Tc in response to a high level of select signals SEL0-SEL3. A flipflop circuit fetches and outputs an output of the selector circuit in synchronization with a clock signal C0. The number of hardware components is reduced in comparison with the conventional case where a select signal generation circuit generates only one select signal SEL, and where a plurality of flipflop circuits and 2-input selector circuits carry out a select and shifting operation of parallel data signals I0-I3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.