Circuit and method for correction of a linear address during 16-bit addressing
US5612911A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 18, 1995 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | May 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device performing arithmetic operations on a plurality of digital inputs to produce an Effective Address and a Linear Address in parallel. The integrated circuit device comprises a first, second and third circuit. The first circuit includes a first adding circuit performs logical operations on the plurality of digital inputs (segment address, scaled index, displacement and segment base) to produce a first plurality of output signals for use in producing the Effective Address and another plurality of output signals to produce an uncorrected Linear Address. The uncorrected Linear Address, if accurate, should be equivalent to the arithmetic sum of the Effective Address and the segment base. Since the first circuit may produce an inaccurate uncorrected Linear Address as detected by a second circuit, the integrated circuit includes a third circuit, controlled by the second circuit, to subsequent modify the uncorrected Linear Address to obtain the Linear Address if the arithmetic sum of the Effective Address and the segment base is not equal to the uncorrected Linear Address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.