Multiple memory bit/chip failure detection
US5612965A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1995 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | Dec 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for efficiently detecting errors in a system having a plurality of memory devices. The present invention uses a single parity bit configuration to detect common data errors caused by faulty memory devices including multiple data errors within one memory device. This is accomplished by effectively turning a multiple bit error detection situation into a single bit error detection situation. Thus, instead of allocating a contiguous block of bits to the same memory unit, the present invention allocates bits across all memory units in a round-robin fashion. The parity domains are defined such that multiple errors within one SRAM can be detected despite only using a single bit parity configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.