Separately clocked processor synchronization improvement
US5613127A · kind A · utility
15Cited by
8References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 2, 1995 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | Jun 2, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/184
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processor apparatus for control functions performed in a redundant manner utilizing separate clocks but correcting for mismatch in timing thereof by causing an interrupt of the processing through software to a "hold" status to allow time for any lagging processors to catch up before starting a next frame of processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.