Adaptive mechanism for efficient interrupt processing
US5613129A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 1994 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | May 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Postponing the interrupt for an I/O event can increase system throughput by amortizing the cost of the interrupt service routine over multiple I/O events. In current systems that provide interrupt postponement, the time parameter is fixed. Fixed values can lead to parameter configuration errors, excessive characterization work to generate parameter values, and a failure to automatically re-configure to system changes or to external load changes. The proposed mechanism measures actual system experience and eliminates the parameter configuration effort by filtering its own experience to derive a target value for interrupt postponement. A current postponement value with the potentially greater variance than the target is used to rapidly respond to abrupt change in offered load. The invention also benefits tasks with real-time deadlines to provide correct system operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.