Data transfer device and multiprocessor system
US5613138A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1994 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | Mar 16, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system for executing distribution, arrangement and collection of array data between a host processor and plural processor elements, control parameter regarding array data to be transferred and an identification number assigned to each data receiver are set beforehand to a data receiver of each processor element. Data sequentially sent out onto a data bus with synchronization with a strobe signal from the data transmitter of the host processor are fetched selectively according to a data transfer allowance signal generated based on the control parameter and the identification number. The fetched data is written into a memory with a discrete address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.