Serial register multi-input multiplexing architecture for multiple chip processor
US5613144A · kind A · utility
26Cited by
22References
16Claims
0Family size
Assignee
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Key dates
| Filing date | May 19, 1995 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | May 19, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.