Reduced power apparatus and method for testing high speed components

US5614838A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Talal K. Jaber · Austin, US
• Steven Schmidt · Blaine, US

Key dates

• Filing date: Nov 3, 1995
• Grant date: Mar 25, 1997
• Expiry date: Nov 3, 2015

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318552
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A system for testing a high speed integrated circuit includes a test device having a test clock with a first maximum frequency for performing level sensitive scan design (LSSD) testing of the integrated circuit device under test, a frequency multiplier circuit for multiplying the test clock signal to a higher second frequency capable of operating the device under test, and a finite state machine for generating a first internal clock for testing the device under test. In a practical embodiment, the internal clock speed may be running at a frequency many multiples of the test clock. Alternatively, a method of testing a device under test (DUT) at design speed includes running a predetermined group of tests with a test device operating at a lower speed than the design speed; incorporating LSSD or boundary scan test techniques in the device under test, together with a frequency multiplying device; generating a global clock for the device under test from the frequency multiplying circuit and using a finite state machine as a synchronizer and pulse generator to control a capture clock with respect to the global clock.