Electrostatic discharge protection apparatus
US5615073A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 1995 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Jun 22, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
A protection system for an integrated circuit includes a protection structure for the input terminals and output terminals that protects against ESD stress in bonding pad to V.sub.SS and bonding pad to V.sub.DD paths, both negative and positive paths. The protection system also includes a protection structure for protecting bonding pad to bonding pad electrical paths and a protection structure for V.sub.DD to V.sub.SS paths. Using all three protection structures in combination provides full protection against ESD events in all possible paths in an integrated circuit. A protection structure isolates an output buffer from the protection structure and encourages stress discharge through the protection structure rather than the output buffer. In addition, a set of design rules is set forth for the design and layout of the output buffer and protection structure including rules pertaining to transistor width, finger width, channel length, contact to gate spacing, and the like which significantly enhance ESD protection. In one embodiment, an electrostatic discharge (ESD) protection circuit connected to a pad of a semiconductor integrated circuit includes an NMOS transistor having a gate a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.