Semiconductor memory device having plural memory mats with centrally located reserve bit or word lines
US5615156A · kind A · utility
8Cited by
5References
9Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | May 27, 1994 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | May 27, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.