Apparatus and method for controlling the initiating of a synchronization protocol for synchronizing a plurality of processors in a multi-processor system
US5615327A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 1995 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Apr 4, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/463
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor (MP) computer sytem which allows target CPU(s) to continue processing instructions while other target CPU(s) are processing instructions of emulation code to reach their end of a Domain Unit of Operation before synchronization. A two-level MP sync is used since the target CPUs must be in between units of operation when the updates occur since a unit of operation can be one instruction or it can be many instructions that together emulate one instruction. Two level MP sync allows CPUs that are going to be serialized to continue to process single instructions (no emulation code) while other target CPUs are in emulation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.