Memory reflection system and method for reducing bus utilization and device idle time in the event of faults
US5615334A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1994 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Oct 7, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory reflection scheme is disclosed including a snarfing agent provided with efficient memory reflection circuitry for snarfing data. The memory reflection circuitry is for snarfing particular data written back from a write back agent to a memory subsystem agent. In response to unsuccessfully snarfing the particular data written back from the write back agent to the memory subsystem agent, the memory reflection circuitry issues a command to read the particular data from the memory subsystem agent. However, the memory reflection circuitry only issues such a command if the write back agent successfully writes back the particular data to the memory subsystem agent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.