Microprocessor having register bank architecture
US5615348A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1994 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Oct 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor having a register bank architecture has n register banks, a memory, a bus for connecting the register bank and the memory, and a bank controller for controlling store/load operations between the register banks and the memory. The controller has a current bank pointer indicating data region of the register banks and the memory during the data store/load operations, and a bank size designation register indicating a bank size to be stored/loaded during the store/load operations. When an address of the current bank pointer is set in an destination operand in an instruction, the controller receives the contents of the current bank pointer and bank size designation register. The controller controls the store operation for the n register banks based on the current bank pointer and the bank size designation register, and changes the content of the current bank pointer with the content of the destination operand in the instruction after the completion of the data store operation, receives the content of the current bank pointer and the content of the bank size designation register, and controls the load operation for the memory by the contents of the current bank pointer an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.