Clock management for power reduction in a video display sub-system
US5615376A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 1994 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Aug 3, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A video sub-system features reduced power consumption by periodically disabling the video controller clocks used for transferring pixel data to a screen. The video clocks are pulsed only when pixel data is being transferred to the screen, during the time that a horizontal line of pixels is being scanned on the screen. The video clocks are not pulsed during the horizontal and vertical blanking periods, when the electron beam in a cathode-ray-tube is being re-traced. The video clocks are also not pulsed during a recovery period for a flat-panel screen. A video memory contains pixel information for the entire screen and is controlled by a memory controller. The memory controller uses a memory clock to transfer all or part of a horizontal line of pixels to a video buffer. The pixel data is then read out of the video buffer to the screen in a serial fashion, synchronized to the video clock. Host data may be written to a host buffer using a bus clock from the host, and then written to the video memory using the memory clock. The memory clock is only pulsed when data is transferred to or from the video memory, or during memory refresh. The memory clock is not pulsed when the video memory …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.