Switched capacitor analog circuits with low input capacitance
US5617093A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1994 |
| Grant date | Apr 1, 1997 |
| Priority date | — |
| Expiry date | Sep 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a circuit cell of a type which transfers packets of charge through the circuit that are proportional to the magnitude of periodic samples of a signal, a technique for maximizing the circuit cell's input impedance, and particularly to minimize its effective input capacitance, by providing a supplemental source to charge its input capacitor to a level that approximates that which a current sample of the input voltage would cause it to reach. This minimizes the amount of input current drawn by the circuit to charge its input capacitor, the input current during one signal sample generally being only an amount required to increase or decrease the charge level of the prior sample which is provided by the supplemental charge source. Thus, the input capacitor may be made large enough to provide a desired signal-to-noise level and sufficient accuracy, while still providing a high impedance input characteristic. In one embodiment, the supplemental charge comes from an output of the circuit. In another embodiment, the supplemental charge comes from an extra amplifier connected to the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.