Clocking mechanism for delay, short path and stuck-at testing
US5617426A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 1995 |
| Grant date | Apr 1, 1997 |
| Priority date | — |
| Expiry date | Feb 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a level sensitive scan design (LSSD) circuit embodiment for testing the behavior of logic circuits, a mechanism is provided for generating a skewed load of data into a set of shift register scan string latches. The nature of the input scan string assures that a certain number of 0 to 1 or 1 to 0 transitions occurs as an input to the block of logic being tested. Furthermore, a mechanism for delaying by one system clock cycle time the capture of information from the logic block in a second shift register scan string provides a mechanism for testing for the occurrence of short paths and long paths while preserving testability for stuck-at faults. Furthermore, all of these advantages are achieved without impacting the traditional stuck-fault test capabilities of the level sensitive scan design methodology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.